Cybersecurity and OSFA Architecture

Huntsville (Ala.)

In this paper, we will present an overview of the patented OS Friendly Microprocessor Architecture (OSFA) and introduce its cyber security features. We are interested in feedback from cyber security professionals, microprocessor developers, and operating system (OS) developers about the hardware computer security features in the OSFA. The OS Friendly Microprocessor Architecture is based on a cache bank memory pipeline. The cache banks and memory cells incorporate Unix-like file permission bits to create a hardware level computer security mechanism. A trusted OS and OSFA hardware system form a separation kernel. The trusted OS configures the security tags (access permission bits) for each cache bank. Any attempt to access a resource outside the bounds of the sandbox defined by the security tags raises a hardware exception handled by the trusted OS. We present our plans for developing a field programmable gate array (FPGA) softcore OSFA based on the RISC-V architecture for test and evaluation.