Ranjan Hebbar

Date of Award


Document Type


Degree Name

Doctor of Philosophy (PhD)


Electrical and Computer Engineering

Committee Chair

A. Milenkovic

Committee Member

B. Earl Wells

Committee Member

David J. Coe

Committee Member

Jeffrey Kulick

Committee Member

Mohammad R. Haider


Computers--Energy consumption., Computers--Performance.


Energy-efficient computing is one of the most important challenges computer designers and operators are facing today, exacerbated by the ever-increasing demands for faster, smaller, lighter, and more affordable computing. The processor is the primary driver of the overall system power consumption of a computer system. Typical power management techniques rely on either running the processor at a fixed clock frequency or utilizing dynamic voltage and frequency scaling (DVFS) techniques that adjust the processor’s clock frequency in runtime based on its current level of activity. In this dissertation, we first describe the results of our measurement-based study that evaluates the impact of the state-of-the-art power management techniques on performance (P), energy efficiency (EE), and their product (PxEE) in an Intel Core i7 processor, running SPEC CPU2017, Parsec-3.0, and SPECpower_ssj2008 benchmark suites. The results of this study indicate that the state-of-the-art DVFS power management techniques heavily favor performance, resulting in poor energy efficiency. For example, we find that the processor operates at the highest clock frequency even when 90% of all processor cycles are stalls, resulting in wasted energy. To remedy this problem, we introduce, implement, and evaluate the effectiveness of four new DVFS-based power management techniques driven by the following metrics derived from the processor’s performance monitoring unit (PMU): (i) the percentage of all pipeline slot stalls (FS-PS), (ii) the percentage of all cycle stalls (FS-TS), (iii) the percentage of memory-related cycle stalls (FS-MS), and (iv) the number of last level cache misses per kilo instructions (FS-LLCM), respectively. The proposed techniques linearly map these metrics into available processor clock frequencies. The results of the experimental evaluation show that the proposed techniques significantly improve EE and PxEE metrics relative to the state-of-the-art approaches. Further, we find that the proposed techniques are especially effective for memory-intensive benchmarks, wherein EE improves from 121% to 183% and PxEE from 100% to 141%. We elucidate the advantages and disadvantages of each of the proposed techniques and offer guidelines on when to use them.



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