Date of Award
2016
Document Type
Thesis
Degree Name
Master of Science in Engineering (MSE)
Department
Electrical and Computer Engineering
Committee Chair
Fat Duen Ho
Committee Member
David Pan
Committee Member
Jia Li
Subject(s)
Gate array circuits., Semiconductor storage devices--Design and construction., Random access memory., Metal oxide semiconductor field-effect transistors.
Abstract
The present study provides the usage of MOSFETs in Adiabatic logic gates with the most nominal transistor length as 180nm. In this thesis, we have compared the performance of 4T-DRAM cells with three different transistor lengths. The main idea of using DRAM cells is that it can store up to 32GB but the present SRAM cells can be manufactured only up to 16MB. The most effective length is the shortest one that we have used in this thesis and it’s power and output voltage accuracy is mentioned throughout the thesis.
Recommended Citation
Krishnamoorthy, Anupriya, "Performance analysis of adiabatic logic gate circuits using 4T dram cells" (2016). Theses. 176.
https://louis.uah.edu/uah-theses/176