Date of Award


Document Type


Degree Name

Master of Science in Engineering (MSE)


Electrical and Computer Engineering

Committee Chair

Fat Duen Ho

Committee Member

David Pan

Committee Member

Jia Li


Gate array circuits., Semiconductor storage devices--Design and construction., Random access memory., Metal oxide semiconductor field-effect transistors.


The present study provides the usage of MOSFETs in Adiabatic logic gates with the most nominal transistor length as 180nm. In this thesis, we have compared the performance of 4T-DRAM cells with three different transistor lengths. The main idea of using DRAM cells is that it can store up to 32GB but the present SRAM cells can be manufactured only up to 16MB. The most effective length is the shortest one that we have used in this thesis and it’s power and output voltage accuracy is mentioned throughout the thesis.



To view the content in your browser, please download Adobe Reader or, alternately,
you may Download the file to your hard drive.

NOTE: The latest versions of Adobe Reader do not support viewing PDF files within Firefox on Mac OS and if you are using a modern (Intel) Mac, there is no official plugin for viewing PDF files within the browser window.