Date of Award
2019
Document Type
Dissertation
Degree Name
Doctor of Philosophy (PhD)
Department
Electrical and Computer Engineering
Committee Chair
Aleksandar Milenkovic
Committee Member
Rhonda Gaede
Committee Member
Mohammad Haider
Committee Member
Tauhidur Rahman
Committee Member
Earl Wells
Subject(s)
Computer programs--Testing, Embedded computer systems, Multiprocessors, Real-time programming
Abstract
Embedded computing systems powered by modern systems-on-a-chip (SoCs) running sophisticated software applications are indispensable in modern communi-cation, transportation, infrastructure, medicine, military, and entertainment. Semi-conductor technology trends have enabled the design of SoCs that often combine multiple processor cores, hardware accelerators, direct memory controllers, and pe-ripheral interfaces, all connected through an on-chip interconnect. Faster, cheaper, and smaller SoCs have in turn enabled new applications that may have tens of mil-lions of lines of code. These trends have led to rising software engineering costs in modern embedded systems that currently account for over 80% of the total engineer-ing costs. Recent studies found that software developers spend over 50% of their time finding and fixing software bugs. Thus, software debugging is one of the most chal-lenging aspects of embedded system development due to growing hardware and software complexity, limited visibility of system components, and tightening time-to-market. Providing powerful debugging tools to software developers is thus critical to expedite software development and improve software reliability. To find software bugs faster, developers often rely on on-chip trace modules with large buffers to capture program execution traces with minimum interference with program execution. However, high volumes of trace data and the high cost of trace modules limit visibility into the system operation to only short program segments that are often insufficient to locate software bugs. This dissertation introduces a new hardware/software technique for capturing and filtering read data value traces in multicores that enables a complete reconstruction of parallel program execution. The proposed technique called mcFiltrate (multicore cache filtered read data trace) utilizes tracking of data reads in data caches and cache coherence protocol states to minimize the number of trace messages that needs to be streamed out of the target platform to the software debugger. The effectiveness of the proposed technique is determined by analyzing the required trace port bandwidth and trace buffer sizes as a function of the data cache size and the number of processor cores. The experimental environment utilizes architectural execution-driven simulator running benchmarks from two suites, Splash2 and Parsec. The results of the experimental evaluation show that the proposed technique significantly reduces the required trace port bandwidth, from 12.2 to 59.6 for a single core processor and from 13.4 to 73.9 times for an octa core processor, when compared to the state-of-the-art Nexus-like read data value tracing. The proposed technique reduces the requirements for the on-chip trace buffers by several orders of magnitude and the number of required trace port pins by up to 16 times when compared to the state-of-the-art Nexus-like tracing. Consequently, mcFiltrate enables continuous on-the-fly data tracing while requiring modest changes on the hardware platform and the software debugger.
Recommended Citation
Ponugoti, Mounika, "Hardware data value tracing in multicores" (2019). Dissertations. 180.
https://louis.uah.edu/uah-dissertations/180