Date of Award

2016

Document Type

Thesis

Degree Name

Master of Science in Engineering (MSE)

Department

Electrical and Computer Engineering

Committee Chair

Aleksandar Milenkovic

Committee Member

Rhonda Kay Gaede

Committee Member

Earl Wells

Subject(s)

Parallel processing (Electronic computers), High performance processors, Debugging in computer science

Abstract

Software testing and debugging represent critical aspects of the design of modern multicore-based embedded computer systems due to growing hardware and software complexity, increased integration, and tightening time-to-market. The existing tracing and debugging techniques offer limited visibility of the system under test or rely on large on-chip buffers and wide trace ports that increase the system cost. This thesis introduces three hardware/software techniques for capturing and filtering load data value traces in multicores. They track memory read accesses in data caches on the target platform and simulate their behavior in the software debugger to significantly reduce the number of trace events that need to be streamed out of the target platform. Our experimental evaluation explores the effectiveness of the proposed techniques by measuring the trace port bandwidth as a function of system parameters. The results show that the proposed techniques significantly reduce the total trace port bandwidth. The improvements relative to the existing Nexus-like load data value tracing range from 10 to 60 times for a single core and from 19 to 74 times for an octa core.

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